The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device provided with an alignment mark (mask aligning trench) used to position a photomask.
In a process for manufacturing a finely miniaturized or highly integrated semiconductor device, especially when performing photolithography, it is important that a photomask be accurately applied to an existing pattern to form the next pattern. Japanese Unexamined Patent Publication No. 11-67620 describes a method of positioning the photomask. In the publication, an alignment mark (mask aligning trench) is formed on a substrate and detected to position a photomask. Normally, the alignment mark is used only to position the photomask.
A prior art semiconductor device has an element partitioning structure that includes an insulative element partitioning film formed through local oxidation of silicon (LOCOS). When patterning a conductive film on a semiconductor substrate having an insulative element partitioning film, a step formed between the insulative element partitioning film and an element forming section functions as the alignment mark. In this case, the step is used to position a photomask on the semiconductor substrate. Thus, an additional process for forming the alignment mark is not necessary.
Due to the further miniaturization and higher integration of recent semiconductor devices, shallow trench isolation (STI) is now being performed in lieu of LOCOS to form an element partitioning structure. However, when forming an alignment mark, STI has the shortcomings described below. Referring to FIGS. 1a to 1f, a process for forming an element partitioning trench through STI will be discussed to understand these shortcomings.
Referring to FIG. 1a, when performing STI, prior to the formation of element partitioning trenches, a silicon oxide film 111′ is applied to a semiconductor substrate 101 and a silicon nitride film 112a is superimposed on the silicon oxide film 111′. Then, lithography is performed to form a resist 113 having a predetermined pattern, which is a pattern of openings used to form the element partitioning trenches.
Subsequently, referring to FIG. 1b, anisotropic etching is performed to etch the silicon nitride film 112a using the resist 113 as a mask. As a result, portions corresponding to the element partitioning trenches are removed from the silicon nitride film 112a thereby defining a silicon nitride film 112b. Anisotropic etching is then performed on the silicon oxide film 111′ and the semiconductor substrate 101 using the silicon nitride film 112b as a mask. This forms element partitioning trenches 140 and a mask aligning trench 150, which is used as an alignment mark, on the semiconductor substrate 101. The element partitioning trenches 140 define element forming sections 120, 130.
Referring to FIG. 1c, high density plasma chemical deposition (HDP-CVD) is performed to form a silicon oxide film 114. The silicon oxide film 114 has recesses formed at portions corresponding to the trenches 140, 150.
Referring to FIG. 1d, lithography is performed to form a resist 115 in the recesses of the silicon oxide film 114. Then, the silicon oxide film 114 is partially etched and removed using the resist 115 as a mask. The step shown in FIG. 1d facilitates flattening (described later) of the surface of the semiconductor substrate 101 when undergoing chemical mechanical polish (CMP). CMP is described in A novel approach for the elimination of the pattern density dependence of CMP for shallow trench isolation, Joost Grillaert et al., CMP-MIC, pp. 313–318, 1998.
Subsequent to the partial removal of the silicon oxide film 114, referring to FIG. 1e, the resist 115 is removed. When performing CMP, the silicon nitride film 112b is used as a stopper film to grind and flatten the silicon oxide film 114 and the silicon nitride film 112b. As a result, the surface of the ground silicon nitride film 112c, the surface of a silicon oxide film 141a implanted in the element partitioning trench 140, and the surface of a silicon oxide film 151a implanted in the mask aligning trench 150 are flush with one another.
The ground silicon nitride film 112c is selectively removed using hot phosphoric acid. The silicon oxide film 211 is then removed by hydrofluoric acid. As a result, element partitions 141b and a mask aligning section 151b are defined on the semiconductor substrate 101. The element partitions 141b and the mask aligning section 151b are formed by the residue of the silicon oxide films 141a, 151a subsequent to the removal of the silicon nitride film 112c and the silicon oxide film 111.
After the formation of the element partitions 141b and the mask aligning section 151b, in accordance with the type of semiconductor device that is to be manufactured, the semiconductor substrate 101 undergoes a washing process and/or an ion implantation process. Then, for example, a conductive film is patterned on the semiconductor substrate 101. When the conductive film is formed through photolithography, the step defined by the mask aligning section 151b and the semiconductor substrate 101 is detected. The step is used as a mark indicating where to position a mask, which is used to form the conductive film pattern, relative to the element forming sections of the semiconductor substrate 101.
During the manufacturing of a semiconductor device in the prior art, when the step between the mask aligning section (mask aligning trench) 151b and the semiconductor substrate 101 is too small, it becomes difficult to accurately detect the step. As a result, the positioning of a mask becomes difficult.
However, it is preferred that the step between the element partitions 141b and the element forming sections be minimized for the miniaturization of a semiconductor device. This is because the focus margin during photolithography becomes smaller as the semiconductor device becomes smaller, and the underlying film is required to have a higher level of flatness to produce patterns with the necessary accuracy.
In the conventional method for manufacturing a semiconductor device, the element partition and the mask aligning section are simultaneously formed. However, these two sections basically have the same structure. Thus, it is difficult to satisfy the two contradicting requirements. Further, an additional process for forming the alignment mark would increase manufacturing costs, which is not desirable.